Integrated semiconductor memories, for example, DRAM (dynamic random access memory) semiconductor memories, generally include a plurality of memory cell arrays, in which memory cells are arranged at the crossover points of word and bit lines. An individual DRAM memory cell is constructed from a selection transistor and a storage capacitor. The selection transistor acts as a controllable switch and is driven by a signal on a word line connected to its control terminal. For a write or read access to the memory cell, the selection transistor is controlled in the on state, so that the storage capacitor is connected to the connected bit line.
The task of semiconductor memories is to reliably store and read out an item of information. A memory cell of the memory cell array is accessed by an address. Erroneous memory processes can be identified by reading and comparing a read data value with the data value to be expected. If, during production of the integrated semiconductor memory, an error is detected during storing and reading the stored data value of a memory cell, the word or bit line connected to the memory cell read in erroneous fashion is replaced, if possible, by a redundant word or bit line. Because the redundant word and bit lines are generally present only in a small number, integrated semiconductor memories can only be repaired up to a certain degree of error.
During the operation of an integrated semiconductor memory that left production as an error-free device, transfer errors can occur when writing data to the memory cell array or when reading data out of the memory cell array. In this case, a distinction is drawn between random and hard transfer errors. Random errors occur, for example, if DRAM memory cells do not retain the charge stored on their storage capacitor until the next refresh, so that the information stored is at least partly lost. Hard transfer errors arise, for example, in a column or row decoder fails. With a hard transfer error, all memory cells addressed via the defective column or row decoder can no longer be accessed without errors.
Error code correction methods (ECC) are used as error correction measures for suppressing signal disturbances during the operation of the integrated semiconductor memory. In case of an error, the stored datum and a datum stamp specifying the number of bit positions of a datum at which errors have occurred and how the errors must be corrected in connection with the information are stored.
However, using an ECC correction method has numerous disadvantages. Thus, the hardware implementation required for the ECC analysis is generally very complex. Even in error-free operation of the memory, it is necessary to provide memory space for the ECC method. Due to the long correction duration of the method, use of ECC methods in long-term operation is suitable only for the correction of randomly occurring individual errors. The method is disproportionately complex for suppressing known hard and frequent cell errors. A further disadvantage is that the complexity of the error analysis hardware and of the required memory redundancy for the ECC calculation is fixed from the outset and thus cannot be adapted to the requirements.
In practice, however, there are numerous cases in which reliably storing and reading out items of information again from the memory cell array are not matters of prime significance. In research and development, for example, there is interest in the functionality of a new circuit component on the semiconductor chip. If it is possible to drastically reduce the error rate of an input or output data record, newly developed products would be available for characterization purposes and possibly for a first application test even if they still had numerous and unrepaired errors in the memory cell array. Consequently, first technology studies could be carried out with as yet unrepaired semiconductor memories without having to account for cell array problems.
An integrated semiconductor memory in which erroneous input and output data, in particular for test and analysis purposes, are corrected on the semiconductor chip without having to carry out comprehensive cell array repairs in the context of a redundancy analysis is desirable. Further, a method for testing an integrated semiconductor memory in which erroneous input and output data are corrected on the semiconductor chip without having to carry out extensive cell array repairs in a redundancy analysis is desirable.